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Tag:performance-optimizationClear

For existing chips in the market, there's a really uncomfortable trade-off between latency and throughput. Chips that are best at throughput have historically been the chips that are based on HPM as the memory... but that hasn't been so good at latency.

Stripe
3d ago

Hardware is massively parallel. You've got tens of billions, hundreds of billions of transistors on your chip, and it takes maybe 100 clock cycles to get from one side of the chip to the other. You can't do a sequential computation involving transistors on both sides of the chip. The hardware is just fundamentally parallel, and you have to take advantage of that.

4d ago

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